Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.


software_version_and_target_device
betaFALSE build_version2708876
date_generatedSun Mar 14 23:46:11 2021 os_platformWIN64
product_versionVivado v2019.2 (64-bit) project_idcff1dbe15b6849e98fd0d16a77eacd7b
project_iteration4 random_id4ad219dea02d558683518e0b6893dd6c
registration_id4ad219dea02d558683518e0b6893dd6c route_designTRUE
target_devicexc7a100t target_familyartix7
target_packagecsg324 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-10610U CPU @ 1.80GHz cpu_speed2304 MHz
os_nameWindows Server 2016 or Windows 10 os_releasemajor release (build 9200)
system_ram16.000 GB total_processors1

vivado_usage
gui_handlers
abstractcombinedpanel_remove_selected_elements=1 abstractsearchablepanel_show_search=2 basedialog_cancel=2 basedialog_ok=42
basedialog_yes=1 boardchooser_board_table=1 cmdmsgdialog_ok=1 constraintschooserpanel_add_existing_or_create_new_constraints=1
constraintschooserpanel_add_files=2 constraintschooserpanel_file_table=2 filesetpanel_file_set_panel_tree=40 flownavigatortreepanel_flow_navigator_tree=24
flownavigatortreepanel_launch_synthesis_run=1 flownavigatortreepanel_reset_synthesis_run=3 gettingstartedview_create_new_project=2 graphicalview_zoom_fit=1
graphicalview_zoom_in=44 graphicalview_zoom_out=37 hduallist_move_selected_items_down=1 hduallist_move_selected_items_up=1
mainmenumgr_file=2 mainmenumgr_project=1 pacommandnames_auto_connect_target=3 pacommandnames_auto_update_hier=4
pacommandnames_close_project=1 pacommandnames_edit_simulation_sets=1 pacommandnames_open_hardware_manager=3 pacommandnames_run_bitgen=4
pacommandnames_set_used_in_prop=2 pacommandnames_simulation_live_break=1 pacommandnames_simulation_live_restart=2 pacommandnames_simulation_live_run=15
pacommandnames_simulation_live_run_all=2 pacommandnames_simulation_reset_behavioral=3 pacommandnames_simulation_run_behavioral=6 pacommandnames_simulation_settings=1
paviews_project_summary=9 programdebugtab_open_target=3 programdebugtab_program_device=5 programdebugtab_refresh_device=2
programfpgadialog_program=5 projectnamechooser_project_name=2 rdicommands_properties=4 rdicommands_unselect_all=1
rdicommands_waveform_save_configuration=10 rdiviews_waveform_viewer=15 setusedinprop_implementation=1 setusedinprop_synthesis=1
simulationobjectspanel_simulation_objects_tree_table=19 simulationscopespanel_simulate_scope_table=8 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=2 srcchooserpanel_add_or_create_source_file=1
srcchooserpanel_target_language=2 srcchoosertable_src_chooser_table=9 srcfileproppanels_simulation=1 srcmenu_ip_hierarchy=5
srcmenu_open_selected_source_files=1 syntheticagettingstartedview_recent_projects=1 taskbanner_close=9 tclconsoleview_tcl_console_code_editor=1
tclobjecttreetable_treetable=5 waveformnametree_waveform_name_tree=103 waveformview_previous_transition=5
java_command_handlers
autoconnecttarget=3 closeproject=1 editproperties=4 editsimulationsets=1
launchprogramfpga=5 newproject=2 openhardwaremanager=3 runbitgen=4
runimplementation=4 runsynthesis=4 setsourceenabled=2 simulationbreak=1
simulationrestart=2 simulationrun=9 simulationrunall=2 simulationrunfortime=15
toolssettings=1 waveformsaveconfiguration=8
other_data
guimode=2
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=6 simulator_language=Mixed srcsetcount=5 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bscane2=1 bufg=2 carry4=15 fdce=20
fdre=124 fdse=2 gnd=15 ibuf=14
lut1=1 lut2=14 lut3=4 lut4=11
lut5=65 lut6=88 obuf=28 ramb18e1=1
ramd32=24 ramd64e=8 rams32=8 vcc=5
pre_unisim_transformation
bscane2=1 bufg=2 carry4=15 fdce=20
fdre=124 fdse=2 gnd=15 ibuf=14
lut1=1 lut2=14 lut3=4 lut4=11
lut5=15 lut6=38 lut6_2=50 obuf=28
ram32m=4 ram64m=2 ramb18e1=1 vcc=5

phys_opt_design_post_place
command_line_options
-aggressive_hold_fix=default::[not_specified] -bram_register_opt=default::[not_specified] -clock_opt=default::[not_specified] -critical_cell_opt=default::[not_specified]
-critical_pin_opt=default::[not_specified] -directive=default::[not_specified] -dsp_register_opt=default::[not_specified] -effort_level=default::[not_specified]
-fanout_opt=default::[not_specified] -hold_fix=default::[not_specified] -insert_negative_edge_ffs=default::[not_specified] -multi_clock_opt=default::[not_specified]
-placement_opt=default::[not_specified] -restruct_opt=default::[not_specified] -retime=default::[not_specified] -rewire=default::[not_specified]
-shift_register_opt=default::[not_specified] -uram_register_opt=default::[not_specified] -verbose=default::[not_specified] -vhfn=default::[not_specified]

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=0 bram_ports_newly_gated=0 bram_ports_total=2 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=144 srls_augmented=0
srls_newly_gated=0 srls_total=0

ip_statistics
kcpsm6_v1_3/1
component_name=kcpsm6 core_container=NA iptotal=1

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
cfgbvs-1=1

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=2 bufgctrl_util_percentage=6.25
bufhce_available=96 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=24 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=12 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=24 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=6 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=6 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=240 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=135 block_ram_tile_fixed=0 block_ram_tile_used=0.5 block_ram_tile_util_percentage=0.37
ramb18_available=270 ramb18_fixed=0 ramb18_used=1 ramb18_util_percentage=0.37
ramb18e1_only_used=1 ramb36_fifo_available=135 ramb36_fifo_fixed=0 ramb36_fifo_used=0
ramb36_fifo_util_percentage=0.00
primitives
bscane2_functional_category=Others bscane2_used=1 bufg_functional_category=Clock bufg_used=2
carry4_functional_category=CarryLogic carry4_used=15 fdce_functional_category=Flop & Latch fdce_used=20
fdre_functional_category=Flop & Latch fdre_used=122 fdse_functional_category=Flop & Latch fdse_used=2
ibuf_functional_category=IO ibuf_used=14 lut1_functional_category=LUT lut1_used=1
lut2_functional_category=LUT lut2_used=14 lut3_functional_category=LUT lut3_used=6
lut4_functional_category=LUT lut4_used=12 lut5_functional_category=LUT lut5_used=63
lut6_functional_category=LUT lut6_used=75 obuf_functional_category=IO obuf_used=28
ramb18e1_functional_category=Block Memory ramb18e1_used=1 ramd32_functional_category=Distributed Memory ramd32_used=24
ramd64e_functional_category=Distributed Memory ramd64e_used=8 rams32_functional_category=Distributed Memory rams32_used=8
slice_logic
f7_muxes_available=31700 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=15850 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=24 lut_as_logic_available=63400 lut_as_logic_fixed=0
lut_as_logic_used=118 lut_as_logic_util_percentage=0.19 lut_as_memory_available=19000 lut_as_memory_fixed=0
lut_as_memory_used=24 lut_as_memory_util_percentage=0.13 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
register_as_flip_flop_available=126800 register_as_flip_flop_fixed=0 register_as_flip_flop_used=144 register_as_flip_flop_util_percentage=0.11
register_as_latch_available=126800 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=63400 slice_luts_fixed=0 slice_luts_used=142 slice_luts_util_percentage=0.22
slice_registers_available=126800 slice_registers_fixed=0 slice_registers_used=144 slice_registers_util_percentage=0.11
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=24 lut_as_logic_available=63400 lut_as_logic_fixed=0
lut_as_logic_used=118 lut_as_logic_util_percentage=0.19 lut_as_memory_available=19000 lut_as_memory_fixed=0
lut_as_memory_used=24 lut_as_memory_util_percentage=0.13 lut_as_shift_register_fixed=0 lut_as_shift_register_used=0
lut_in_front_of_the_register_is_unused_fixed=0 lut_in_front_of_the_register_is_unused_used=16 lut_in_front_of_the_register_is_used_fixed=16 lut_in_front_of_the_register_is_used_used=13
register_driven_from_outside_the_slice_fixed=13 register_driven_from_outside_the_slice_used=29 register_driven_from_within_the_slice_fixed=29 register_driven_from_within_the_slice_used=115
slice_available=15850 slice_fixed=0 slice_registers_available=126800 slice_registers_fixed=0
slice_registers_used=144 slice_registers_util_percentage=0.11 slice_used=57 slice_util_percentage=0.36
slicel_fixed=0 slicel_used=36 slicem_fixed=0 slicem_used=21
unique_control_sets_available=15850 unique_control_sets_fixed=15850 unique_control_sets_used=16 unique_control_sets_util_percentage=0.10
using_o5_and_o6_fixed=0.10 using_o5_and_o6_used=16 using_o5_output_only_fixed=16 using_o5_output_only_used=0
using_o6_output_only_fixed=0 using_o6_output_only_used=8
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=1 bscane2_util_percentage=25.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
pcie_2_1_available=1 pcie_2_1_fixed=0 pcie_2_1_used=0 pcie_2_1_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7a100tcsg324-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=divider_4_top -verilog_define=default::[not_specified]
usage
elapsed=00:00:56s hls_ip=0 memory_gain=662.598MB memory_peak=960.691MB

xsim
command_line_options
-sim_mode=default::behavioral -sim_type=default::