Index of /ee254/Verilog

 Name                                                                                   Last modified      Size  Description
 Parent Directory                                                                                            -   
 0_Verilog_Main_Points_of_the_6_Lectures.pdf                                            2018-08-28 15:19  8.2M  
 1_Verilog_Introduction.avi                                                             2012-09-08 16:51  309M  
 1_Verilog_Introduction_mht.jnt                                                         2012-09-08 14:40  6.7M  
 1_Verilog_Introduction_mht.pdf                                                         2012-09-08 22:06  5.7M  
 2_module_DataTypes_in_Verilog.avi                                                      2012-09-09 23:16  157M  
 2_module_DataTypes_in_Verilog.jnt                                                      2012-09-09 22:35  1.1M  
 2_module_DataTypes_in_Verilog.pdf                                                      2012-09-09 23:18  2.2M  
 3_behavioral_vs_structural_Verilog.avi                                                 2012-09-10 00:10   76M  
 3_behavioral_vs_structural_Verilog.jnt                                                 2012-09-09 23:45  392K  
 3_behavioral_vs_structural_Verilog.pdf                                                 2012-09-09 23:21  1.5M  
 4_Sequential_Statements_in_Verilog.avi                                                 2012-09-10 08:48  294M  
 4_Sequential_Statements_in_Verilog.jnt                                                 2012-09-10 07:39  2.3M  
 4_Sequential_Statements_in_Verilog.pdf                                                 2012-09-10 23:24  4.3M  
 5_blocking_non_blocking.avi                                                            2011-09-05 15:24  167M  
 5_blocking_non_blocking.pdf                                                            2020-02-06 16:54  6.3M  
 6_RTL_coding_style.avi                                                                 2012-09-13 08:14  115M  
 6_RTL_coding_style.jnt                                                                 2012-09-13 08:25  3.2M  
 6_RTL_coding_style.pdf                                                                 2012-09-13 23:28  3.3M  
 EE201L_Just_the_Special_counter_mixing_blocking_non_blocking_r1.pdf                    2020-02-06 06:43   69K  
 EE254L_RTL_coding_style_verilog.pdf                                                    2018-01-20 12:05  200K  
 EE354L_HW3_Gradescope_Assignment.docx                                                  2025-09-13 18:54  145K  
 EE354L_HW3_Gradescope_Assignment.pdf                                                   2025-09-13 19:06  176K  
 EE354L_Review_of_Narrow_Clock_Divisible_by_7_Exam_Questions_Fall2021_Sp2023.mp4        2023-12-10 14:23  146M  
 EE354L_Review_of_Narrow_Clock_Divisible_by_7_Exam_Questions_Fall2021_Sp2023_melted.pdf 2023-12-10 14:57  5.3M  
 Parity_Generator.zip                                                                   2021-02-13 14:24  3.2K  
 Verilog_Exam_Questions_Exercises_only.pdf                                              2023-09-26 09:16  1.6M  
 Verilog_Exam_Questions_Solutions_only.pdf                                              2023-09-26 09:14  2.2M  
 ee201L_sync_counter_mix_of_blocking_and_non_blocking_assignment.docx                   2017-02-03 17:29  133K  
 ee201L_sync_counter_mix_of_blocking_and_non_blocking_assignment.pdf                    2017-02-03 17:30  198K  
 ee254L_sync_counter_mix_of_blocking_and_non_blocking.zip                               2013-09-26 11:20  6.0K  
 ee254_divider_simple.zip                                                               2012-09-13 12:04  5.8K